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Publications > Conference Papers

Conference Papers

  1. H. Zheng. "A Coordinated Reachability Analysis Method for Modular Verification of Asyn- chronous Designs." Accepted by IEEE International High Level Design Validation and Test Workshop, November, 2009.
  2. S. Roy, N. Ranganathan, and S. Katkoori. "Exploration of Compiler Optimization Techniques for Enhancing Power Gating." To appear in Proceedings of IEEE International Symposium on Circuits and Systems, 2009.
  3. H. Thapliyal and N. Ranganathan, ”Concurrently Testable FPGA Design for Molecular QCA Using Conservative Reversible Logic Gate." To appear in Proc. of the 2009 Intl. Symp. on Circuits and Systems, Taipei, May 2009.
  4. H. Zheng, H. Yao, T. Yoneda. Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs." IEEE Computer Society Annual Symposium on VLSI, May, 2009.
  5. H. Thapliyal and N. Ranganathan. ”Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits.” Proc. of the 22nd Intl. Conf. on VLSI Design, Delhi, India, Jan 2009.
  6. K. Bhattacharya and N. Ranganathan. "A New Placement Algorithm for Reduction of Soft Errors in Standard Cell Based Design of Nanometer Circuits.” In Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 2009.
  7. K. Bhattacharya and N. Ranganathan. ”RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits.” In Proc. of Intl. Conf. on VLSI Design, 2009.
  8. K. Bhattacharya and N. Ranganathan. ”A Unified Gate Sizing Formulation for Optimizing Soft Error Rate, Cross-talk Noise and Power under Process Variations.” To appear in Proc. of ISQED, 2009.
  9. R. Hyman, K. Bhattacharya and N. Ranganathan. ”A Strategy for Soft Error Reduction in Multi-core Designs.” To appear in Proc. of ISCAS, 2009.
  10. K. Bhattacharya, M. Venkataraman and N.Ranganathan. ”A VLSI System Architecture for Optical Flow Computation.” To appear in Proc. of ISCAS, 2009.
  11. U. Gupta and N. Ranganathan. ”A Microeconomic Approach to Multi-Objective Spatial Clustering.” Proc. of IEEE International Conference on Pattern Recognition, 2008.
  12. H. Sankaran, S. Katkoori. “Bus Binding, Re-ordering, and Encoding for Crosstalk-producing Switching Activity Minimization during High Level Synthesis.” Accepted for 4th IEEE Symposium on Electronic Design, Test, and Applications (DELTA 2008), Hong Kong, January 2008.
  13. H. Thapliyal and N. Ranganathan. ”Testable Reversible Latches for Molecular QCA.” To appear in Proc. 8th Intl. Conf. on Nanotechnology (IEEE NANO 2008), Aug. 2008 (Invited Paper).
  14. V. Mahalingam and N. Ranganathan. "A Fuzzy Optimization Approach for Process Variation Aware Buffer Insertion and Driver Sizing." Proc. IEEECS Annual Symposium on VLSI (ISVLSI), Montpellier, France, April 2008.
  15. H. Sankaran and S. Katkoori. “Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis.” Accepted at IEEECS Annual Symposium on VLSI, April 2008, Montepellier, France.
  16. N. Ranganathan, U. Gupta and V. Mahalingam. "Simultaneous Optimization of Total Power, Crosstalk Noise, and Delay Under Uncertainty in." Proc. Great Lakes Symposium on VLSI (GLSVLSI), Pages 171-176, 2008.
  17. K. Bhattacharya and N. Ranganathan. ”A Linear Programming Formulation for Security-Aware Gate Sizing.” Proc. of GLSVLSI, pages 273-278, 2008 (Ranked within Top 6 Papers, nominated for Best Paper Award based on blind review).
  18. U. Gupta and N. Ranganathan. ”An Expected-Utility Based Approach to Variation Aware VLSI Optimization Under Scarce Information." Proc. of ISLPED, Aug. 2008.
  19. K. Bhattacharya and N. Ranganathan, ”Reliability-centric Gate Sizing with Simultaneous Optimization of Soft Error Rate, Delay and Power”, Proc. of ISLPED, 2008.
  20. K. Bhattacharya, S. Kim and N. Ranganathan, ”Improving the Reliability of On-chip L2 Cache Using Redundancy”, Proc. of the ICCD, pp 224-229, 2007.
  21. N. Hanchate and N. Ranganathan, ”Integrated Gate and Wire Sizing at Post Layout Level”, Proc. IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 2007.
  22. N. Hanchate and N. Ranganathan, ”Statistical Gate Sizing for Yield Enhancement at Post Layout Level”, Proc. of the IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 2007.
  23. V. Mahalingam and N. Ranganathan, ”Variation Aware Timing based Placement using Fuzzy Programming”, Proc. IEEE International Symposium on Quality Electronic Design, ISQED, Pages 327-332, Mar 2007.
  24. S. Roy, S. Katkoori and N. Ranganathan, ”A Compiler-Based Leakage Reduction Technique For Power- Gating Functional Units in Embedded Microprocessors”, Proc. 20th International Conference on VLSI Design, Pages 215-220, Jan 2007.
  25. D. Mu, T. Xia, H. Zheng. Data Dependent Jitter Characterization Based on Fourier Analysis", Proceedings of IEEE International Symposium of Defect and Fault Tolerance in VLSI Systems (DFT). November 2006.
  26. V. Mahalingam and N. Ranganathan, J.E. Harlow,”A Novel Approach for Variation Aware Power Minimzation during Gate Sizing”, Proc. IEEE International Symposium on Low Power Electronic Design, pp. 174-179, ISLPED Oct 2006.
  27. U. Gupta and N. Ranganathan, ”Social Fairness in Multi-Emergency Resource Management”, Proc. of IEEE International Symposium on Technology and Society, ISTAS‘06, June 8-10 2006.
  28. N. Hanchate and N. Ranganathan, ”A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise”, Proc. Intl. Conf. on VLSI Design, pp. 283-290, Jan 2006 (ranked 1 out of 360 submissions, BEST PAPER AWARD winner).
  29. A. Oruganti and N. Ranganathan, ”Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs by Probabilistic Analysis of Vth Variation, Proc. 19th Intl. Conf. on VLSI Design, pp. 766-769, Jan 2006.
  30. V. Sairaman, N. Ranganathan, N. Singh, ”An Automatic Code Generation Tool for Partitioned Software in Distributed Systems”, Proc. Intl. Conf. on VLSI Design, pp. 477-480, Jan 2006.
  31. V. Mahalingam and N. Ranganathan, ”An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition”, Proc. Intl. Conf. on VLSI Design, pp. 393-398, Jan 2006.
  32. U. Gupta and N. Ranganathan, ”FIRM: A Game Theory Based Multi-Crisis Management System for Urban Environments”, Proc. of the American Nuclear Society Intl. Conf. on Sharing Solutions for Emergencies and Hazardous Environments, pp: 595-602, Feb, 2006.
  33. N. Hanchate and N. Ranganathan, ”Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization”, Proc. of 7th Intl. Symp. on Quality Electronic Design, pp. 92-97, Mar. 2006.
  34. N. Ranganthan, R. Namballa, and N. Hanchate, ”CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL”, Proc. of IEEE Computer Society Annual Symposium on VLSI, Mar. 2006.
  35. V. Mahalingam and N. Ranganathan, ”A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection”, Proc. of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp. 180-185, May 2005.
  36. S. P. Mohanty, N. Ranganathan and K. Balakrishnan, ”Design of a Low Power Image Watermarking Encoder using Dual Voltage and Frequency”, in Proceedings of the 18th IEEE International Conference on VLSI Design (VLSID) , pp. 153-158, 2005 (blind review, 97 regular papers accepted out of 352 submissions, acceptance rate - 28
  37. S. Bhanja, K. Lingasubramanian and N. Ranganathan, ”Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks, 18th International Conference in VLSI Design, pp. 586- 591, 2005.
  38. Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan, ” A Stimulus-Free Graphical Probabilistic Switching Model For Sequential Circuits Using Dynamic Bayesian Networks”, Proc. 41st Design Automation Conference (DAC), Pages 773-796, June 2004.
  39. R. Namballa, N. Ranganathan and A. Ejnioui, ”Control and Data Flow Graph Extraction for High Level Synthesis”, Proc. of IEEECS Annual Symposium on VLSI, Lafayette, pp. 187-192, Feb 19-20, 2004.
  40. A. K. Murugavel and N. Ranganathan, ”Gate Sizing and Buffer Insertion using Economic Models for Power Optimization”, Proc. Intl. Conf. on VLSI Design, pp. 195-200, Jan 2004 (BEST PAPER AWARD winner).
  41. N. Hanchate
    42. and N. Ranganathan, ”A New Technique for Leakage Reduction in Digital CMOS Circuits”, Proc. Intl. Conf. on VLSI Design, Jan 2004.
  42. A. K. Murugavel and N. Ranganathan, ”Game Theoretic Modeling of Voltage and Frequency Scaling During Behavioral Synthesis,” Proc. Intl. Conf. on VLSI Design, pp. 670-673, Jan 2004.
  43. S. P. Mohanty, N. Ranganathan and R. K. Namballa, ”VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design”, Proceedings of the 17th IEEE International Conference on VLSI Design (VLSID), pp. 1063-1068, 2004 (blind review, 92 full papers accepted out of 330 submissions, acceptance rate - 27.8
  44. S. P. Mohanty, N. Ranganathan and S. K. Chappidi, ” ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis”, Proceedings of the 17th IEEE International Conference on VLSI Design (VLSID), pp. 745-748, 2004 (blind review, 92 full papers and 46 short papers accepted out of 330 submissions, acceptance rate - 41.8
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