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Publications > Journal Publications

Journal Publications

  1. H. Zheng, Compositional Reachability Analysis for Eficient Modular Verification of Asynchronous Designs, IEEE Transactions on Compter-Aided Designs of Integrate Circuits and Systems, Accepted for Publication, 2009.
  2. H. Zheng, H. Yao, T. Yoneda, Modular Model Checking of Large Asynchronous Designs with Eficient Abstraction Refinement, IEEE Transactions on Computers, Accepted for Publication,2009.
  3. H. Yao, H. Zheng, Automated Interface Refinement for Compositional Verification, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(3), 433-446, 2009.
  4. H. Thapliyal and N. Ranganathan, ” Reversible Logic Based Concurrently Testable Latches for Molecular QCA”, To appear in IEEE Transactions on Nanotechnology, 2009.
  5. U. Gupta and N. Ranganathan, ”A Game Theoretic Approach for Simultaneous Compaction and Equi- Partitioning of Spatial Datasets”, To appear in IEEE Transactions on Knowledge and Data Engineering, 2009.
  6. V. Mahalingam and N. Ranganathan, Timing based Placement Considering Uncertainty due to Process Variations, To appear in IEEE Transactions on VLSI Systems, 2009.
  7. S. Roy, N. Ranganathan, and S. Katkoori. A Framework for Power Gating Functional Units in Embedded Microprocessors. To appear in IEEE Transactions on VLSI Systems, 2009.
  8. K. Bhattacharya, N. Ranganathan and S. Kim, A Framework For Correction of Multi-bit Soft Errors in L2 Caches Based on Redundancy, to appear in IEEE Transactions on VLSI Systems, Jan 2009.
  9. V. Mahalingam, K. Bhattacharya, N. Ranganathan, H. Chakravarthula, R. Murphy and K. Pratt, ”A VLSI Architecture and Algorithm forLucas-Kanade Based Optical Flow Computation”, to appear in IEEE Transactions on VLSI Systems, 2009.
  10. V. Mahalingam, N. Ranganathan and J. E. Harlow, ”A Fuzzy Optimization Approach for Gate Sizing in the Presence of Process Variations”, IEEE Transactions on VLSI Systems, 16(8), Pp. 975-984, Aug. 2008.
  11. H. Zheng, J. Ahrens, T. Xia, A Compositional Method with Failure-Preserving Abstractions for Asynchronous Design Verification, IEEE Transactions on Computer-Aided Design of In- tegrated Circuits and Systems, 27(7), 2008.
  12. T. Xia, H. Zheng, Timing Jitter Characterization for Mixed-Signal Production Test Using the Interpolation Algorithm, IEEE Transactions on Industrial Electronics, 54(2), 2007.
  13. S.P. Mohanty, E. Kougianos and N. Ranganathan, ” A VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking”, IET Computers & Digital Techniques (Proceedings of IEE), 1(5), Pp. 600-611, Sept. 2007.
  14. U. Gupta and N. Ranganathan, ”Multi-Event Crisis Management Using Non-Cooperative Multi-Step Games”, IEEE Transactions on Computers, 56(5), pages 1-13, May 2007.
  15. N. Ranganathan, U. Gupta, R. Shetty and A.K. Murugavel, ”An Automated Decision Support System Based on Game Theoretic Optimization for Emergency Management in Urban Environments”, Journal of Homeland Security and Emergency Management, Berkeley Electronic Press, Pages 1-25, 2007 (Listed in Top 5 Downloaded Papers in the Journal).
  16. K.P. Subbalakshmi, R. Chandramouli and N. Ranganathan, ”A sequential distinguisher for covert channel identification,” International Journal of Network Security , 5(3), pages 274-282, Nov 2007.
  17. V. Mahalingam and N. Ranganathan, ”Improving Accuracy in Mitchell’s Logarithmic Multiplication using Operand Decomposition”, IEEE Transactions on Computers, 55(12), Pages 1523-1535, Dec 2006.
  18. H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda, Verification of Timed Circuits with Failure Directed Abstractions, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(3), 2006.
  19. N. Hanchate and N. Ranganathan, ”Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory”, IEEE Transactions on Computers, 55(8), Pages 1011-1023, Aug. 2006.
  20. N. Hanchate and N. Ranganathan, ”A Game Theoretic Framework for Multimetric Optimization of Interconnect Delay, Power and Crosstalk Noise During Wiresizing”, ACM Trans. on Design Automation of Electronic Systems, 11(3), Pages 711-739, July 2006.
  21. S. Bhanja, K. Lingasubramanian and N. Ranganathan, ”A Stimulus-free Graphical Probabilistic Switch- ing Model for Sequential Circuits using Dynamic Bayesian Networks”, ACM Transactions on Design Automation of Electronic Systems, 11(3), Pages 773-796, July 2006.
  22. S. P. Mohanty, N. Ranganathan, and S. K. Chappidi, ”ILP Models for Simultaneous Energy and Transient Power Minimization during Behavioral Synthesis”, ACM Transactions on Design Automation of Electronic Systems 11(1), Pages 186-212, Jan 2006.
  23. S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, ”A Dual Voltage-Frequency VLSI Chip for Image Watermarking in DCT Domain”, IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 53, No. 5, Pages 394-398, May 2006.
  24. S. P. Mohanty, N. Ranganathan, and R. K. Namballa, ”A VLSI Architecture for Visible Watermarking Design”, IEEE Transactions on Very Large Scale Integration in a Secure Still Digital Camera Systems (TVLSI), Vol. 13, No. 8, August 2005, pp. 1002-1012.
  25. S. P. Mohanty and N. Ranganathan, ”Simultaneous Peak and Average Power Minimization during Datapath Scheduling”, IEEE Transactions on Circuits and Systems Part I (TCAS-I), Vol. 52, No. 6, June 2005, pp. 1157-1165.
  26. S. P. Mohanty and N. Ranganathan, ”Energy Efficient Datapath Scheduling using Multiple Voltages and Dynamic Clocking”, ACM Transactions on Design Automation of Electronic Systems, 10(2), Pages 330-353, April 2005.
  27. S. P. Mohanty and N. Ranganathan, ”A Framework for Energy and Transient Power Reduction during Behavioral Synthesis”, IEEE Transactions on VLSI Systems, 12(6), June 2004, pp. 562-572.
  28. S. Bhanja and N. Ranganathan,”Cascaded Bayesian Inferencing for Switching Activity Estimation”, IEEE Transactions on VLSI Systems, 12(12), Pages 1360-1370, Dec 2004.
  29. A. Murugavel and N. Ranganathan, ”A Game-Theoretic Approach for Power Optimization during Behavioral Synthesis”, IEEE Transactions on VLSI Systems, 11(6), Pages 1031-1043, Dec 2003.
  30. A. Murugavel and N. Ranganathan, ”A Real Delay Switching Activity Simulator Based on Petri Net Modeling”, IEEE Transactions on VLSI Systems, 11(5), Pages 921-927, October 2003.
  31. S. Bhanja and N. Ranganathan, ”Switching Activity Estimation of VLSI Circuits Using Bayesian Networks”, IEEE Transactions on VLSI Systems, 11(4), Pp. 558-567, August 2003.
  32. A. Ejnioui and N. Ranganathan, ”Routing on Field Programmable Switch Matrices”, IEEE Transactions on VLSI Systems, 11(2), Pp. 283-287, April 2003.
  33. A. Ejnioui and N. Ranganathan,”Multi-terminal net routing for partial crossbar-based multi-FPGA systems”, IEEE Transactions on VLSI Systems, 11(1), Pp. 71-78, Feb 2003.
  34. R. Chandramouli, K.P. Subbalakshmi, and N. Ranganathan, “Channel-adaptive stochastic rate control for low bit rate wireless video transmission,” Special issue on Video Objects: representation, creation, coding, transmission, manipulation and retrieval, Pattern Recognition Letters, 25(7), Pages 793-806, 2004.
  35. N. Hanchate and N. Ranganathan, ”LECTOR: A Novel Technique for Leakage Reduction in CMOS VLSI Circuits”, IEEE Transactions on VLSI Systems, 12(2), Pages 196-205, Feb 2004.
  36. H. Zheng, E. Mercer, C. Myers, Modular Verification of Timed Systems Using Automatic Abstraction, IEEE Transactions on CAD, September, 2003.
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